1. Field of the Invention
The present invention relates generally to manufacturing processes requiring lithography and, more particularly, to monitoring of lithographic and etch process conditions used in microelectronics manufacturing which is particularly useful for monitoring pattern features with dimensions on the order of less than 0.5 micron.
2. Description of Related Art
Control of a lithographic imaging process requires the optimization of exposure and focus conditions in lithographic processing of product substrates or wafers. Likewise, it is also important to optimize etching and other parameters on product wafers. Generally, because of the variations in exposure and focus, patterns developed by lithographic processes must be continually monitored or measured to determine if the dimensions of the patterns are within acceptable range. The importance of such monitoring increases considerably as the resolution limit, which is usually defined as minimum features size resolvable, of the lithographic process is approached. The patterns being developed in semiconductor technology are generally in the shape of lines both straight and with bends, having a length dimension equal to and multiple times the width dimension. The width dimension, which by definition is the smaller dimension, is of the order of 0.1 micron to greater than 1 micron in the current leading semiconductor technology. Because the width dimension is the minimum dimension of the patterns, it is the width dimension that challenges the resolution limits of the lithographic process. In this regard, because width is the minimum and most challenging dimension to develop, it is the width dimension that is conventionally monitored to assess performance of the lithographic process. The term xe2x80x9cbiasxe2x80x9d is used to describe the change in a dimension of a feature from its nominal value. Usually the bias of interest is the change in the smallest of the dimensions of a given feature. Further, the term xe2x80x9cbiasxe2x80x9d is invariably used in conjunction with a process such as resist imaging, etching, developing etc. and described by terms such as image bias, etch bias, print bias, etc.
Prior solutions to the above problems entail the collection and analysis of critical dimension measurements using SEM metrology on multiple pattern types at multiple locations within the chip, and from chip-to-chip. This method is slow, expensive and error-prone. It usually requires the exposure of multiple focus-exposure and etching matrices on product wafers.
More recent lithographic monitoring improvements have been in optical metrology which rely on human or machine-read visual measurement of targets which employ arrays of elements having line widths and spacing below the wavelength of the light used to make the measurements. Improvements in monitoring bias in lithographic and etch processes used in microelectronics manufacturing have been disclosed in U.S. Pat. Nos. 5,712,707; 5,731,877; 5,757,507; 5,805,290; 5,953,128; 5,965,309; 5,976,740; 6,004,706 and 6,027,842, the disclosures of which are hereby incorporated by reference. In U.S. Pat. No. 5,757,507, a method of monitoring features on a target using an image shortening phenomenon was disclosed. In U.S. Pat. No. 5,712,707, targets and measurement methods using verniers were disclosed to measure bias and overlay error. In these applications, the targets comprised arrays of spaced, parallel elements having a length and a width, with the ends of the elements forming the edges of the array. While the targets and measurement methods of these applications are exceedingly useful, they rely on the increased sensitivity to process variation provided by image shortening. Some of these types of targets use image shortening effects to make the visual measurements of even though the individual array elements are not resolvable. Examples of such targets are disclosed in the aforementioned U.S. patents. Such targets permit visual monitoring of pattern features of arbitrary shape with dimensions on the order of less than 0.5 micron, and which is inexpensive to implement, fast in operation and simple to automate. These determine bias to enable in-line lithography/etch control using optical metrology, and wherein SEM and/or AFM metrology is required only for calibration purposes.
While these methods provide good visual monitoring, electrical monitoring methods to measure pattern dimensions in lithographic processes would provide useful precision, speed and automation. Some of such processes are disclosed in the article by Christopher P. Ausschnitt entitled Electrical Measurements For Characterizing Lithography, VLSI Electronics Microstructure Science, Vol. 16 (1987). Such methods include the use of electrical test structures in the characterization and control of lithography and etch processes. As described in the above reference, the electrical test structures and methods used to date are applicable only to the measurement of line width. Furthermore, they do not enable the distinguishing of dose and focus effects.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide an improved monitor and evaluation method for determining exposure and focus conditions in lithographic processing of semiconductor structures using electrical measurements of image shortening for both line and space patterns.
It is another object of the invention to provide electrically testable structures to measure, characterize and monitor image shortening.
It is another object of the present invention to provide an electrically testable structure to solve relative dose and focus problems in lithographic processing.
A further object of the invention is to provide a method of electrically testing lithographically applied layers for optimum dose and focus.
It is yet another object of the present invention to provide a method of evaluating focus-exposure parameters which is easy and inexpensive to utilize.
It is a further object of the present invention to provide a method and monitor which electrically measures focus and exposure in lithographically deposited patterns, and which utilize little space on a wafer substrate.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.
The above and other objects and advantages, which will be apparent to one of skill in the art, are achieved in the present invention which is directed to, in a first aspect, a monitor for electrically testing image shortening of a pattern, preferably energy beam dose or focus of a layer formed on a substrate by lithographic processing. The monitor comprises a substrate having in a lithographically formed layer an array of electrically conductive elements comprising a plurality of spaced, substantially parallel elements having a length and a width, with the individual elements being electrically connected, and the lengths of the elements being sensitive to dose and focus of an energy beam in lithographically forming the layer. The monitor further includes at least one pad electrically connected to the array to apply current through the array elements. Upon applying a voltage and driving a current across the array elements, the suitability of dose or focus of the lithographically formed layer may be determined by the resistance of the array. Preferably, ends of the individual elements are aligned along essentially straight lines to form an array edge.
In another aspect, the present invention provides a monitor for electrically testing image shortening of a pattern, preferably energy beam dose or focus of a layer formed on a substrate by lithographic processing comprising a substrate; a first lithographically formed layer comprising a first electrically conductive area; and a second lithographically formed layer on the substrate. The second lithographically formed layer includes an array of electrically conductive elements having greater conductivity than the first electrically conductive area comprising a plurality of spaced, substantially parallel elements having a length and a width, with ends of the individual elements being aligned to form first and second opposing array edges, and with the individual elements being electrically connected along the first array edge and unconnected across the second array edge, such that the lengths of the elements are sensitive to dose and focus of an energy beam in lithographically forming the layer. The second lithographically formed layer further includes a second electrically conductive area having greater conductivity than the first electrically conductive area and having an edge spaced from the second array edge, with the second array edge and the edge of the second electrically conductive area overlying the first conductive area in the first lithographic layer. Upon applying a voltage and driving a current between the first array edge of the array of electrically conductive elements and the second conductive area so that current flows through the array elements, the first conductive area and the second conductive area, the suitability of dose or focus of the second lithographically formed layer may be determined by the resistance of the array.
Preferably, the ends of the individual elements are aligned along essentially straight lines to form the array edges, and the second array edge and the edge of the second electrically conductive area are essentially parallel. The monitor may further include a pad electrically connected to the array to apply current through the array elements.
In a further aspect, the present invention provides a monitor for electrically testing image shortening of a pattern, preferably energy beam dose or focus of a layer formed on a substrate by lithographic processing comprising a substrate; a first lithographically formed layer comprising a first electrically conductive area; and a second lithographically formed layer on the substrate. The second lithographically formed layer includes a first array of electrically conductive elements having greater conductivity than the first electrically conductive area comprising a plurality of spaced, substantially parallel elements having a length and a width, with ends of the individual elements being aligned to form first and second opposing array edges, and the individual elements being electrically connected along the first array edge and unconnected across the second array edge, such that the lengths of the elements are sensitive to dose and focus of an energy beam in lithographically forming the layer. The second lithographically formed layer also includes a second array of electrically conductive elements having greater conductivity than the first electrically conductive area comprising a plurality of spaced, substantially parallel elements having a length and a width, with ends of the individual elements being aligned to form first and second opposing array edges, and the individual elements being electrically connected along the first array edge and unconnected across the second array edge, such that the lengths of the elements are sensitive to dose and focus of an energy beam in lithographically forming the layer. The second edge of the second array is spaced from the second edge of the first array, with the second edges of the first and second arrays overlying the first conductive area in the first lithographic layer. Upon applying a voltage and driving a current between first array edges of the first and second arrays of electrically conductive elements so that current flows through the first array elements, the first conductive area and the second array elements, the suitability of dose or focus of the second lithographically formed layer may be determined by the resistance of the first and second arrays.
Preferably, the ends of the individual elements are aligned along essentially straight lines to form the array edges, and the second array edges of the first and second arrays of electrically conductive elements are essentially parallel. The monitor may further include a first pad electrically connected to the first array to apply current through the first array elements and a second pad electrically connected to the second array to apply current through the second array elements. The first electrically conductive area of the first lithographically formed layer may underlie the first and second arrays of electrically conductive elements.
In yet another aspect, the present invention provides a monitor for electrically testing image shortening of a pattern, preferably energy beam dose or focus of a layer formed on a substrate by lithographic processing comprising a substrate; and a lithographically formed layer on the substrate having an array of electrically conductive elements having greater conductivity than the first electrically conductive area. The array comprises a plurality of spaced, substantially parallel elements having a length and a width, with ends of the individual elements being aligned to form first and second opposing array edges, and the individual elements being electrically connected by a central conductive element between the first and second array edges and unconnected across the second array edge, such that the lengths of and spaces between the elements being sensitive to dose and focus of an energy beam in lithographically forming the layer. Upon applying a voltage and driving a current across opposing ends of the central conductive element so that current flows through the central conductive element, the suitability of dose or focus of the lithographically formed layer may be determined by the resistance of the central conductive element. The monitor may further include a pair of pads electrically connected to opposing ends of the array to apply current through the central conductive element.
Another aspect of the present invention provides a monitor for electrically testing image shortening of a pattern, preferably energy beam dose or focus of a layer formed on a substrate by lithographic processing comprising a substrate; a first lithographically formed layer comprising a first electrically conductive area; and a second lithographically formed layer on the substrate. The second lithographically formed layer includes a first array of electrically conductive elements having greater conductivity than the first electrically conductive area comprising a plurality of spaced, substantially parallel elements having a length and a width, with ends of the individual elements being aligned to form first and second opposing array edges, and the individual elements being electrically connected along the first array edge and unconnected across the second array edge, such that the lengths of the elements are sensitive to dose and focus of an energy beam in lithographically forming the layer. The second lithographically formed layer also includes a second array of electrically conductive elements having greater conductivity than the first electrically conductive area comprising a plurality of spaced, substantially parallel elements having a length and a width, with ends of the individual elements being aligned to form first and second opposing array edges, and the individual elements being electrically connected along the first array edge and unconnected across the second array edge, such that the lengths of the elements are sensitive to dose and focus of an energy beam in lithographically forming the layer. The second edge of the second array is spaced from the second edge of the first array, and the second edges of the first and second arrays overlie the first conductive area in the first lithographic layer. The second lithographically formed layer further includes a third array of electrically conductive elements comprising a plurality of spaced, substantially parallel elements having a length and a width, with ends of the individual elements being aligned to form first and second opposing array edges, and the individual elements being electrically connected by a central conductive element between the first and second array edges and unconnected across the second array edge, such that the lengths of and spaces between the elements are sensitive to dose and focus of an energy beam in lithographically forming the layer. One end of the central conductive element is electrically connected to first array edge of the second array of electrically conductive elements. Upon applying a voltage and driving a current between the first array edge of the first array of electrically conductive elements and the other end of the central conductive element so that current flows through the first array elements, the first conductive area, the second array elements and the central conductive element, the suitability of dose or focus of the second lithographically formed layer may be determined by the resistance of the first and second arrays and the central conductive element.
The monitor may further include a first pad electrically connected to the first array edge of the first array to apply current through the first array elements and a second pad electrically connected to the other end of the central conductive element to apply current through the central conductive element. The third array of electrically conductive elements has greater conductivity than the first electrically conductive area of the first lithographically formed layer and the first electrically conductive area underlies the first, second and third arrays of electrically conductive elements.